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general description the MAX5072 is a dual-output dc-dc converter with inte- grated high-side n-channel power mosfets. each output can be configured either as a buck converter or a boost converter. the MAX5072 is designed to manage the power requirements of xdsl modems. the wide 5.5v to 23v input voltage range allows for the use of inexpensive ac adapters to power the device in xdsl modem appli- cations. each output is programmable down to 0.8v in the buck mode and up to 28v in the boost mode with an out- put voltage accuracy of ?%. in the buck mode, convert- er 1 and converter 2 can deliver 2a and 1a, respectively. the output switching frequency of each converter can be programmed from 200khz to 2.2mhz to avoid harmonics in the xdsl frequency band of operation. each output operates 180 out-of-phase, thus reducing input-capaci- tor ripple current, size, and cost. a sync input facilitates external frequency synchronization. moreover, a clkout output provides out-of-phase clock signal with respect to converter 2, allowing four-phase operation using two MAX5072 ics in master-slave configuration. the MAX5072 includes an internal digital soft-start that reduces inrush current, eliminates output-voltage over- shoot, and ensures monotonic rise in output voltage dur- ing power-up. the device includes a power-good output and power-on reset as well as manual reset. in addition, each converter output can be shut down individually. the MAX5072 features a "dying gasp" output, which goes low when the input voltage drops below a preprogrammed voltage. protection features include output short-circuit protection for buck mode and maximum duty-cycle limit for boost operation, as well as thermal shutdown. the MAX5072 is available in a thermally enhanced 32-pin thin qfn package that can dissipate 2.7w at +70? ambi- ent temperature. the device is rated for operation over the -40? to +85? extended, or -40? to +125? automotive temperature range. applications xdsl modems xdsl routers point-of-load dc-dc converters features ? 4.5v to 5.5v or 5.5v to 23v input supply voltage range ? 0.8v (buck) to 28v (boost) output voltage ? two independent output dc-dc converters with internal power mosfets ? each output can be configured in buck or boost mode ? i out1 and i out2 of 2a and 1a (respectively) in buck mode ? 180 out-of-phase operation ? clock output for four-phase operation ? switching frequency programmable from 200khz to 2.2mhz ? digital soft-start and independent converter shutdown ? sync input, power-on reset, manual reset, and power-fail output ? short-circuit protection (buck)/maximum duty- cycle limit (boost) ? thermal shutdown ? thermally enhanced 32-pin thin qfn package dissipates up to 2.7w at +70c MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output ________________________________________________________________ maxim integrated products 1 pin configuration ordering information 19-3503; rev 2; 2/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available 24 23 22 21 20 19 18 1234567 10 11 12 13 14 15 16 31 30 29 28 27 26 25 MAX5072 thin qfn top view source1 pgood1 source1 pgnd sgnd pgnd source2 32 source2 fsel1 bst1/vdd1 drain1 drain1 en1 fb1 comp1 17 rst mr bypass vl vl v+ osc pfi 9 sync comp2 fb2 8 pfo en2 drain2 drain2 bst2/vdd2 clkout part temp range pin-package pkg code MAX5072etj -40 c to +85 c 32 thin qfn-ep* (5mm x 5mm) t3255-4 * ep = exposed pad. ordering information continued at end of data sheet.
MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v+ = vl = 5.2v or v+ = 5.5v to 23v, en_ = vl, sync = gnd, i vl = 0, pgnd = sgnd, c bypass = 0.22?, c vl = 4.7? (ceramic), r osc = 10k ? (circuit of figure 1), t a = t j = t min to t max , unless otherwise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to pgnd............................................................-0.3v to +25v sgnd to pgnd .....................................................-0.3v to +0.3v vl to sgnd...................-0.3v to the lower of +6v or (v+ + 0.3v) bst1/vdd1, bst2/vdd2, drain_, pfo, rst , pgood1 to sgnd .................................................................-0.3v to +30v bst1/vdd1 to source1, bst2/vdd2 to source2 ....................................-0.3v to +6v source_ to sgnd................................................-0.6v to +25v en_ to sgnd ................................................-0.3v to (vl + 0.3v) clkout, bypass, osc, fsel1, comp1, comp2, pfi, mr, sync, fb_ to sgnd....-0.3v to (vl + 0.3v) source1, drain1 peak current ..............................5a for 1ms source2, drain2 peak current ..............................3a for 1ms vl, bypass to sgnd short circuit............................continuous continuous power dissipation (t a = +70?) 32-pin thin qfn (derate 21.3mw/? above +70?) .....2758mw* package junction-to-case thermal resistance ( j c ).......2?/w operating temperature ranges: MAX5072etj (t min to t max )...........................-40? to +85? MAX5072atj (t min to t max ).........................-40? to +125? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? * as per jedec51 standard. parameter symbol conditions min typ max units system specifications (note 2) 5.5 23 input voltage range v+ vl = v+ 4.5 5.5 v operating supply current i q vl unloaded, no switching, v fb_ = 1v, v+ = 12v, r osc = 60k ? 2.2 1.2 ma en_ = 0, mr , pfo, and pgood_ floating, v+ = 12v, r osc = 60k ? ( MAX5072etj) 0.6 1.4 v+ standby supply current i stby en_ = 0, mr , pfo, and pgood_ floating, v+ = 12v, r osc = 60k ? ( MAX5072atj) 0.6 1.4 ma v+ = vl = 5v 82 v+ = 12v 80 efficiency v out1 = 3.3v at 1.5a, v out2 = 2.5v at 0.75a (f sw = 1.25mhz) v+ = 16v 78 % startup/vl regulator vl undervoltage lockout trip level uvlo vl falling 3.95 4.1 4.25 v vl undervoltage lockout hysteresis 175 mv vl output voltage vl v+ = 5.5v to 23v, i source = 0 to 40ma 4.9 5.2 5.5 v bypass output i bypass = 0, r osc = 60k ? ( MAX5072etj) 1.98 2.00 2.02 bypass voltage v bypass i bypass = 0, r osc = 60k ? ( MAX5072atj) 1.975 2.00 2.025 v bypass load regulation ? v bypass 0 i bypass 50?, r osc = 60k ? 0210mv soft-start digital ramp period internal 6-bit dac 2048 f osc clock cycles soft-start steps 64 steps
MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output _______________________________________________________________________________________ 3 electrical characteristics (continued) (v+ = vl = 5.2v or v+ = 5.5v to 23v, en_ = vl, sync = gnd, i vl = 0, pgnd = sgnd, c bypass = 0.22?, c vl = 4.7? (ceramic), r osc = 10k ? (circuit of figure 1), t a = t j = t min to t max , unless otherwise noted.) (note 1) parameter symbol conditions min typ max units voltage-error amplifier fb_ input bias current i fb 250 na 0? t a +70? 0.792 0.8 0.808 -40? t a +85? 0.788 0.8 0.812 fb_ input voltage set point -40? t j +125? (MAX5072atj only) 0.788 0.8 0.812 v 0? to +85? 1.25 2.00 2.70 -40? to +85? 1.2 2.0 2.9 fb_ to comp_ transconductance g m -40? to +125? (MAX5072atj only) 1.2 2.0 2.9 ms internal mosfets i switch = 100ma, v bst1/vdd1 to v source1 = 5.2v (MAX5072etj) 195 290 i switch = 100ma, v bst1/vdd1 to v source1 = 5.2v (MAX5072atj) 195 330 i switch = 100ma, v bst1/vdd1 to v source1 = 4.5v (MAX5072etj) 200 315 on-resistance converter 1 r on1 i switch = 100ma, v bst1/vdd1 to v source1 = 4.5v (MAX5072atj) 200 350 m ? i switch = 100ma, v bst2/vdd2 to v source2 = 5.2v 330 630 on-resistance converter 2 r on2 i switch = 100ma, v bst2/vdd2 to v source2 = 4.5v 350 690 m ? minimum converter 1 output current i out1 v out1 = 3.3v, v+ = 12v (note 3) 2 a minimum converter 2 output current i out2 v out2 = 2.5v, v+ = 12v (note 3) 1 a converter 1 mosfet leakage current i lk1 en1 = 0v, v ds = 23v 10 ? converter 2 mosfet leakage current i lk2 en2 = 0v, v ds = 23v 10 ? internal switch current limit v+ = 12v (MAX5072etj) 2.3 3 4.3 current-limit converter 1 i cl1 v+ = 12v (MAX5072atj) 2.3 3 4.6 a MAX5072etj 1.38 1.8 2.10 current-limit converter 2 i cl2 MAX5072atj 1.38 1.8 2.10 a
MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output 4 _______________________________________________________________________________________ electrical characteristics (continued) (v+ = vl = 5.2v or v+ = 5.5v to 23v, en_ = vl, sync = gnd, i vl = 0, pgnd = sgnd, c bypass = 0.22?, c vl = 4.7? (ceramic), r osc = 10k ? (circuit of figure 1), t a = t j = t min to t max , unless otherwise noted.) (note 1) parameter symbol conditions min typ max units internal oscillator/sync sync = sgnd, f sw = 1.25mhz 84 86 95 maximum duty cycle d max sync = sgnd, f sw = 2.2mhz 84 86 95 % switching frequency range f sw each converter 200 2200 khz switching frequency f set r osc = 10k ?, each converter 1125 1250 1375 khz switching frequency accuracy 5.6k ? r osc 56k ? , 1%, each converter -15 +15 % sync frequency range f sync sync input frequency is twice the individual converter frequency 400 4400 khz sync high threshold v synch 2.4 v sync low threshold v syncl 0.8 v sync input min pulse width t syncin 100 ns clock output phase delay clkout phase rosc = 60k ? , 1%, with respect to converter 2/source2 waveform 45 degrees sync to source 1 phase delay sync phase rosc = 60k ? , 1% 45 degrees clock output high level v clkouth vl = 5.2v, sourcing 5ma 4 v clock output low level v clkoutl vl = 5.2v, sinking 5ma 0.4 v fsel1 fsel1 input high threshold v ih v+ = vl = +5.2v 2.4 v fsel1 input low threshold v il v+ = vl = +5.2v 0.8 v en_ inputs en_ input high threshold v ih v+ = vl = +5.2v 2.4 1.8 v en_ input low threshold v il v+ = vl = +5.2v 1.2 0.8 v en_ bias current i b(en) 250 na manual reset ( mr ) and power-on-reset ( rst ) mr minimum pulse width t mr 10 ? mr glitch immunity maximum glitch pulse width allowed for rst to remain high 100 ns mr to rst propagation delay t md 1s mr input high threshold v ih v+ = vl = +5.2v 2.4 v mr input low threshold v il v+ = vl = +5.2v 0.8 v mr internal pullup resistor r mr 44 k ? power-on-reset threshold v th rst goes high 180ms after v out1 and v out2 cross this threshold 90 92.5 95 % v out fb_ to rst propagation delay t fd fb overdrive from 0.8v to 0.6v 1.1 ? rst active timeout period t rp 140 200 360 ms i sink = 3ma (MAX5072etj) 0.4 rst output voltage v rst_ i sink = 3ma (MAX5072atj) 0.52 v rst output leakage current i rstlk v+ = vl = 5.2v, v rst = 23v, v fb _ = 0.8v 1 a
MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output _______________________________________________________________________________________ 5 electrical characteristics (continued) (v+ = vl = 5.2v or v+ = 5.5v to 23v, en_ = vl, sync = gnd, i vl = 0, pgnd = sgnd, c bypass = 0.22?, c vl = 4.7? (ceramic), r osc = 10k ? (circuit of figure 1), t a = t j = t min to t max , unless otherwise noted.) (note 1) parameter symbol conditions min typ max units power-good output (pgood1) pgood1 threshold pgood1 vth pgood1 goes high after v out crosses pgood1 threshold 90 92.5 95 % v out i sink = 3ma (MAX5072etj) 0.4 pgood1 output voltage v pgood1 i sink = 3ma (MAX5072atj) 0.52 v p go od 1 o utp ut leakag e c ur r ent i lkp good 1 v + = v l = 5.2v , v p good 1 = 23v , v f b1 = 1v 1a dying gasp power-fail input (pfi), power-fail output (pfo) pfi trip level v th pfi falling 0.76 0.78 0.80 v pfi hysteresis v thh 20 mv pfi input bias current i b(pfi) v pfi = 0.75v 500 na pfi glitch immunity 100mv overdrive 35 ? pfi to pfo propagation delay t pfd 50mv overdrive 35 ? i sink = 3ma (MAX5072etj) 0.4 pfo output low voltage v pfo i sink = 3ma (MAX5072atj) 0.52 v pfo output leakage current i lkpfo v+ = vl = 5.2v, v pfo = 5.5v, v pfi = 1v 1 a thermal management thermal shutdown t shdn junction temperature +150 ? thermal hysteresis t hyst junction temperature 30 ? note 1: specifications at -40 c are guaranteed by design and not production tested. note 2: operating supply range (v+) is guaranteed by vl line regulation test. connect v+ to vl for 5v operation. note 3: output current may be limited by the power dissipation of the package, see the power dissipation section in the applications information .
typical operating characteristics (v+ = vl = 5.2v, t a = +25?, unless otherwise noted.) MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output 6 _______________________________________________________________________________________ 0 20 10 40 30 60 50 70 90 80 100 0.2 0.6 0.8 1.0 0.4 1.2 1.4 1.6 1.8 2.0 output1 efficiency (buck converter) vs. load current MAX5072 toc01 load (a) efficiency (%) v in = 12.0v v in = 16.0v v in = 5v v out = 3.3v f sw = 2.2mhz 0.2 0.4 0.5 0.3 0.6 0.7 0.8 0.9 1.0 output2 efficiency (buck converter) vs. load current MAX5072 toc02 load (a) 0 20 10 40 30 60 50 70 90 80 100 efficiency (%) v in = 12.0v v in = 16.0v v in = 5v v out = 2.5v f sw = 2.2mhz output2 efficiency (boost converter) vs. load current MAX5072 toc03 load (a) 0.14 0.08 0.02 0.20 0 20 10 40 30 60 50 70 90 80 100 efficiency (%) v in = 5.0v v in = 3.3v v out = 12v f sw = 2.2mhz 3.40 3.35 3.30 3.25 3.20 0 1.0 0.5 1.5 2.0 output1 voltage (buck converter) vs. load current MAX5072 toc04 load (a) output1 voltage (v) 2.45 2.50 2.55 2.60 0 0.25 0.50 0.75 1.00 output2 voltage (buck converter) vs. load current MAX5072 toc05 load (a) output2 voltage (v) 5.00 5.15 5.10 5.05 5.20 5.25 5.30 5.35 5.40 5.45 5.50 0.1 1.1 0.6 1.6 2.1 2.6 vl output voltage vs. converter switching frequency MAX5072 toc06 switching frequency (f sw )(mhz) vl (v) both converters switching v in = 23v v in = 5.5v 0 0.10 0.05 0.20 0.15 0.30 0.25 0.35 01.0 0.5 1.5 2.0 2.5 vl dropout voltage vs. each converter switching frequency MAX5072 toc07 switching frequency (f sw ) (mhz) dropout voltage (v) v in = 4.5v v in = 5v v in = 5.5v each converter switching frequency vs. r osc MAX5072 toc08 r osc (k ? ) switching frequency (f sw ) (mhz) 40 1 10 0.1 80 0 20 60 each converter switching frequency vs. temperature MAX5072 toc09 temperature ( c) switching frequency (f sw ) (mhz) 50 1.00 10.00 0.10 150 -50 0 100 2.2mhz 1.25mhz 0.6mhz 0.3mhz
typical operating characteristics (continued) (v+ = vl = 5.2v, t a = +25?, unless otherwise noted.) MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output _______________________________________________________________________________________ 7 1ms/div line-transient response (buck converter) v in 5v/div MAX5072 toc10 0v v out1 = 3.3v/1.5a ac-coupled 200mv/div v out2 = 2.5v/0.75a ac-coupled 200mv/div 100 s/div converter 1 load-transient response (buck converter) i out1 1a/div MAX5072 toc11 0a v out1 = 3.3v ac-coupled 200mv/div 100 s/div converter 2 load-transient response (buck converter) i out2 500ma/div MAX5072 toc12 0a v out1 = 3.3v ac-coupled 400mv/div v out2 = 2.5v ac-coupled 100mv/div 2ms/div soft-start/soft-stop MAX5072 toc13 enable 5v/div 0v v out1 = 3.3v/1a 2v/div 0v v out2 = 2.5v/0.5a 2v/div 0v 100 s/div load-transient response (boost converter) MAX5072 toc14 v out1 = 3.3v ac-coupled 200mv/div 0a v out2 = 12v ac-coupled 200mv/div i out2 50ma/div v+ = vl = 5.2v 40ms/div rst active timeout period MAX5072 toc15 v out1 5v/div v out2 2v/div enable 5v/div rst 5v/div 0v 0v 0v 0v 100ns/div out-of-phase operation MAX5072 toc16 input ripple ac-coupled 20mv/div source 2 5v/div source 1 5v/div 0v 0v 0v clkout 5v/div
typical operating characteristics (continued) (v+ = vl = 5.2v, t a = +25?, unless otherwise noted.) MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output 8 _______________________________________________________________________________________ v+ switching supply current (i supply ) vs. temperature MAX5072 toc19 i supply (ma) 10 15 20 25 30 35 5 temperature ( c) 92 59 26 -7 -40 125 f sw = 2.2mhz f sw = 1.25mhz f sw = 600khz f sw = 300khz 3.20 3.26 3.24 3.22 3.28 3.30 3.32 3.34 3.36 3.38 3.40 -50 0 50 100 150 output1 voltage (buck converter) vs. temperature MAX5072 toc20 temperature ( c) output1 voltage (v) no load 50% load 2.60 2.55 2.50 2.45 2.40 -50 50 0 100 150 output2 voltage (buck converter) vs. temperature MAX5072 toc21 temperature ( c) output2 voltage (v) no load 50% load output load current limit vs. temperature MAX5072 toc22 temperature ( c) output current limit (a) 65 30 -5 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 1.00 -40 100 v in = 5.5v f sw = 2.2mhz output1 output2 200ns/div external synchronization MAX5072 toc17 v out1 ripple ac-coupled 20mv/div source 1 5v/div 0v 0v 0v clkout 5v/div sync 5v/div v+ standby supply current (i stby ) vs. temperature MAX5072 toc18 temperature ( c) i stby (ma) 92 59 26 -7 0.6 1.0 1.4 1.8 0.2 -40 125 r osc = 10k ? r osc = 60k ?
MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output _______________________________________________________________________________________ 9 typical operating characteristics (continued) (v+ = vl = 5.2v, t a = +25?, unless otherwise noted.) pin description pin name function 1 clkout clock output. clkout is 45?phase-shifted with respect to converter 2 (source2, figure 3). connect clkout (master) to the sync of a second MAX5072 (slave) for a four-phase converter. 2 bst2/vdd2 buck converter operation?ootstrap flying-capacitor connection for converter 2. connect bst2/vdd2 to an external ceramic capacitor and diode according to the standard application circuit (figure 1). boost converter operation?river bypass capacitor connection. connect a low-esr 0.1? ceramic capacitor from bst2/vdd2 to pgnd (figure 9). 3, 4 drain2 connection to converter 2 internal mosfet drain. buck converter operation?se the mosfet as a high-side switch and connect drain2 to the input supply. boost converter operation?se the mosfet as a low-side switch and connect drain2 to the inductor and diode junction (figure 9). 5 en2 acti ve- h i g h e nab l e inp ut for c onver ter 2. d r i ve e n 2 l ow to shut d ow n conver ter 2, d r i ve e n 2 hi g h for nor m al op er ati on. u se e n 2 i n conj uncti on w i th e n 1 for sup p l y seq uenci ng . c onnect to v l for al w ays- on op er ati on. 6 fb2 feed b ack inp ut for c onver ter 2. c onnect fb2 to a r esi sti ve d i vi d er b etw een conver ter 2 s outp ut and s gn d to ad j ust the outp ut vol tag e. to set the outp ut vol tag e b el ow 0.8v , connect fb2 to a r esi sti ve vol tag e- d i vi d er fr om by p as s to r eg ul ator 2 s outp ut ( fi g ur e 6) . s ee the s etti ng the o utp ut v ol tag e secti on. 7 comp2 compensation connection for converter 2. see the compensation section to compensate converter 2? control loop. 8 pfo d yi ng gasp c om p ar ator outp ut. the p fo op en- d r ai n outp ut g oes l ow w hen p fi fal l s b el ow the 0.78v r efer ence. 9 sync external clock synchronization input. connect sync to a 400khz to 4400khz clock to synchronize the switching frequency with the system clock. each converter frequency is one half the frequency applied to sync. connect sync to sgnd when not used. 10 pfi dying gasp comparator noninverting input. connect a resistor-divider from the input supply to pfi. pfi forces pfo low when v pfi falls below 0.78v. the pfi comparator has a 20mv (typ) hysteresis. this is an uncommitted comparator and can be used for any protection feature such as ovp or power-good. 100ms/div manual reset (mr) MAX5072 toc23 v out1 = 3.3v 5v/div mr 5v/div rst 5v/div v out2 = 2.5v 5v/div 400ns/div four-phase operation (see figure 3) MAX5072 toc24 0v 0v 0v source 1 (master) source 2 (master) source 1 (slave) source 2 (slave)
MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output 10 ______________________________________________________________________________________ pin description (continued) pin name function 11 osc oscillator frequency set input. connect a resistor from osc to sgnd (r osc ) to set the switching frequency (see the oscillator section). set r osc for equal to or lower oscillator frequency than the sync input frequency when using external synchronization (0.2f sync < f osc < 1.2f sync ). r osc is still required when an external clock is connected to the sync input. 12 v+ input supply voltage. v+ voltage range from 5.5v to 23v. connect the v+ and vl together for 4.5v to 5.5v input operation. bypass with a minimum 0.1? ceramic capacitor to sgnd. 13, 14 vl internal 5.2v linear regulator output. use vl to drive the high-side switch at bst1/vdd1 and bst2/vdd2. bypass vl with a 0.1? capacitor to pgnd and a 4.7? ceramic capacitor to sgnd. 15 bypass 2.0v output. bypass to sgnd with a 0.22? or greater ceramic capacitor. 16 mr active-low manual reset input. drive mr low to initiate a reset. rst remains asserted while mr is low and for 180ms (t rp ) after mr returns high. mr requires no external debounce circuitry. mr is internally pulled high by a 44k ? resistor and can be left open if not used. 17 rst open-drain reset output. rst remains low when either output voltage is below 92.5% of its regulation point or while mr is low. after soft-start is completed and both outputs exceed 92.5% of their nominal output voltage, rst becomes high impedance after a 180ms (typ) delay. rst remains high impedance as long as both outputs maintain regulation. 18 comp1 compensation connection for converter 1 (see the compensation section) 19 fb1 feed b ack inp ut for c onver ter 1. c onnect fb1 to a r esi sti ve d i vi d er b etw een conver ter 1 s outp ut and s gn d to p r og r am the outp ut vol tag e. to set the outp ut vol tag e b el ow 0.8v , connect fb1 to a r esi sti ve vol tag e- d i vi d er fr om by p as s to r eg ul ator 1 s outp ut ( fi g ur e 6) . s ee the s etti ng the o utp ut v ol tag e secti on. 20 en1 acti ve- h i g h e nab l e inp ut for c onver ter 1. d r i ve e n 1 l ow to shut d ow n conver ter 1, d r i ve e n 1 hi g h for nor m al op er ati on. u se e n 1 i n conj uncti on w i th e n 2 for sup p l y seq uenci ng . c onnect to v l for al w ays- on op er ati on. 21, 22 drain1 connection to the converter 1 internal mosfet drain. buck conver ter op er ati on use the m os fe t as a hi g h- si d e sw i tch and connect d rain 1 to the i np ut sup p l y. boost converter operation?se the mosfet as a low-side switch and connect drain1 to the inductor and diode junction. 23 bst1/vdd1 buck converter operation?ootstrap flying-capacitor connection for converter 1. connect bst1/vdd1 to an external ceramic capacitor and diode according to the standard application circuit (figure 1). boost converter operation?river bypass capacitor connection. connect a low-esr 0.1? ceramic capacitor from bst1/vdd1 to pgnd (figure 9). 24 fsel1 converter 1 frequency select input. connect fsel1 to vl for normal operation. connect fsel1 to sgnd to reduce converter 1? switching frequency to 1/2 converter 2? switching frequency (converter 1 switching frequency will be 1/4 the sync frequency). do not leave fsel1 unconnected. 25 pgood1 converter 1 power-good output. open-drain output goes low when converter 1? output falls below 92.5% of its set regulation voltage. use pgood1 and en2 to sequence the converters. 26, 27 source1 connection to the converter 1 internal mosfet source. buck converter operation?onnect source1 to the switched side of the inductor as shown in figure 1. boost converter operation?onnect source1 to pgnd.
MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output ______________________________________________________________________________________ 11 pin description (continued) pin name function 28, 30 pgnd power ground. connect rectifier diode anode, input capacitor negative, output capacitor negative, and vl bypass capacitor returns to pgnd. 29 sgnd s i g nal g r ound . c onnect s g n d to the exp osed p ad . c onnect s g n d and p g n d tog ether at a si ng l e p oi nt. 31, 32 source2 connection to the converter 2 internal mosfet source. buck converter operation?onnect source2 to the switched side of the inductor as shown in figure 1. boost converter operation?onnect source2 to pgnd (figure 9). ep sgnd exposed paddle. connect to sgnd. solder ep to the sgnd plane for better thermal performance. pgood1 vl clock out output 2.5v/1a output 3.3v/2a vl vl vl pgnd sgnd pfo system clock v in = 5.5v to 23v p reset input 32 31 30 29 28 27 26 9 101112131415 18 19 20 21 22 23 24 7 6 5 4 3 2 1 bst2/vdd2 clkout drain2 drain2 en2 on off fb2 comp2 8 pfo source2 pgnd sgnd sgnd pgnd source1 25 pgood1 fsel1 ep bst1/vdd1 drain1 drain1 en1 fb1 comp1 17 rst bypass vl 16 mr manual reset vl v+ osc pfi sync on off vout1 dying gasp sgnd* MAX5072 *connect pgnd and sgnd together at one point near the return terminals of the v+ and vl bypass capacitors. figure 1. MAX5072 dual buck regulator application circuit
MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output 12 ______________________________________________________________________________________ detailed description pwm controller the MAX5072 converter uses a pulse-width modulation (pwm) voltage-mode control scheme for each out-of- phase controller. it is nonsynchronous rectification and uses an external low-forward-drop schottky diode for rectification. the controller generates the clock signal by dividing down the internal oscillator or the sync input when driven by an external clock, so each con- troller? switching frequency equals half the oscillator frequency (f sw = f osc / 2). an internal transconduc- tance error amplifier produces an integrated error volt- age at the comp pin, providing high dc accuracy. the voltage at comp sets the duty cycle using a pwm comparator and a ramp generator. at each rising edge of the clock, converter 1? high-side n-channel mosfet turns on and remains on until either the appropriate or maximum duty cycle is reached, or the maximum cur- rent limit for the switch is detected. converter 2 oper- ates out-of-phase, so the second high-side mosfet turns on at each falling edge of the clock. in the case of buck operation (figure 1), during each high-side mosfet? on-time, the associated inductor current ramps up. during the second half of the switch- ing cycle, the high-side mosfet turns off and forward biases the schottky rectifier. during this time, the source voltage is clamped to 0.4v (v d ) below ground. the inductor releases the stored energy as its current ramps down, and provides current to the out- put. the bootstrap capacitor is also recharged from the inductance energy when the mosfet turns off. the cir- cuit goes in discontinuous conduction mode operation at light load, when the inductor current completely dis- charges before the next cycle commences. under overload conditions, when the inductor current exceeds the peak current limit of the respective switch, the high- side mosfet turns off quickly and waits until the next clock cycle. in the case of boost operation, the mosfet is a low- side switch (figure 9). during each on-time, the induc- tor current ramps up. during the second half of the switching cycle, the low-side switch turns off and for- ward biases the schottky diode. during this time the drain voltage is clamped to 0.4v (v d ) above v out_ and the inductor provides energy to the output as well as replenishes the output capacitor charge. internal oscillator/out-of-phase operation the internal oscillator generates the 180 out-of-phase clock signal required by each regulator. the internal oscillator frequency is programmable from 400khz to 4.4mhz using a single 1% resistor at r osc . use the fol- lowing equation to calculate r osc : where f osc is the internal oscillator frequency in hertz and r osc in ohms. the two independent regulators in the MAX5072 switch 180 out-of-phase to reduce input filtering require- ments, to reduce electromagnetic interference (emi), and to improve efficiency. this effectively lowers com- ponent cost and saves board space, making the MAX5072 ideal for cost-sensitive applications. with dual synchronized out-of-phase operation, the MAX5072? high-side mosfets turn on 180 out-of- phase. the instantaneous input current peaks of both regulators do not overlap, resulting in reduced rms rip- ple current and input voltage ripple. this reduces the required input capacitor ripple current rating, allows for fewer or less expensive capacitors, and reduces shielding requirements for emi. the out-of-phase wave- forms in the typical operating characteristics demon- strate synchronized 180 out-of-phase operation. synchronization (sync)/clock output (clkout) the main oscillator can be synchronized to the system clock by applying an external clock (f sync ) at sync. the f sync frequency must be twice the required oper- ating frequency of an individual converter. use a ttl logic signal for the external clock with at least a 100ns pulse width. r osc is still required when using external synchronization. program the internal oscillator fre- quency so 0.2f sync < f osc < 1.2f sync . the rising edge of f sync synchronizes the turn-on edge of internal mosfet (see figure 3). where f osc is the internal oscillator frequency in hertz and r osc in ohms, f osc = 2 x f sw . two MAX5072s can be connected in master-slave con- figuration for four ripple-phase operation. the MAX5072 provides a clock output (clkout) that is 45 phase- shifted with respect to the internal switch turn-on edge. feed the clkout of the master to the sync input of the slave. the effective input ripple switching frequency shall be four times the individual converter? switching frequency. when driving the master converter using external clock at sync, set the clock duty cycle to 50% for a 90 phase-shifted operation. r 25 10 f osc 9 osc = r 25 10 f osc 9 osc =
MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output ______________________________________________________________________________________ 13 oscillator comp2 fb2 source2 vdd2 reset comp1 pgood1 source1 drain1 v+ bypass f_sel1 en1 sync cko osc pfi en2 drain2 n converter 2 vl oscillator 35 s glitch immunity vref debounce main oscillator digital soft-start converter 1 ldo q q vref frequency divider v cc v cc 180ms delay v cc 0.5v ref 0.92v ref v ref f sw /4 frequency foldback dead-time control pfo fb1 vl mr vl open drain bst1/vdd1 MAX5072 q reset2 bst2/vdd2 figure 2. functional diagram
MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output 14 ______________________________________________________________________________________ frequency select (fsel1) sometimes it is necessary to operate the converter at a lower switching frequency to keep the losses low for lower power dissipation. however, it is not possible to have different frequencies for two converters operating out-of-phase. also, frequency beating may occur if the individual converter frequencies are not selected care- fully. to avoid these issues, and still achieve the lower power dissipation in the package, the MAX5072 pro- vides a frequency select (fsel1) pin. connecting fsel1 to ground reduces the switching frequency of converter 1 to 1/2 the switching frequency of converter 2 and 1/4th of the internal oscillator switching frequen- cy. in this case, the input capacitor ripple frequency is 1.5 times the converter 2 switching frequency and also has unsymmetrical ripple waveform. sync source1 (master) clkout (master) source2 (master) source1 (slave) source2 (slave) clkout (slave) c in (ripple) sync phase clkout phase sync sync slave master v+ output4 output3 drain2 source2 drain1 source1 clkout clkin v+ output2 output1 cin v in drain2 source2 drain1 source1 duty cycle = 50% figure 3. synchronized controllers
MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output ______________________________________________________________________________________ 15 input voltage (v+)/internal linear regulator (vl) all internal control circuitry operates from an internally regulated nominal voltage of 5.2v (vl). at higher input voltages (v+) of 5.5v to 23v, vl is regulated to 5.2v. at 5.5v or below, the internal linear regulator operates in dropout mode, where vl follows v+. depending on the load on vl, the dropout voltage can be high enough to reduce vl below the undervoltage lockout (uvlo) threshold. for input voltages of less than 5.5v, connect v+ and vl together. the load on vl is proportional to the switch- ing frequency of converter 1 and converter 2. see the vl dropout voltage vs. each converter switching frequency graph in the typical operating characteristics . for input voltage ranges higher than 5.5v, use the internal regulator. bypass v+ to sgnd with a low-esr, 0.1? or greater ceramic capacitor placed close to the MAX5072. current spikes from vl may disturb internal circuitry powered by vl. bypass vl with a low-esr, ceramic 0.1? capacitor to pgnd and a 4.7? capacitor to sgnd. undervoltage lockout/soft-start the MAX5072 includes an undervoltage lockout with hysteresis and a power-on-reset circuit for smooth con- verter turn-on and monotonic rise of the output voltage. the rising uvlo threshold is internally set to 4.3v with a 175mv hysteresis. hysteresis at uvlo eliminates ?hattering?during startup. when vl drops below uvlo, the internal switches are turned off and rst is forced low. digital soft-start/soft-stop is provided internally to reduce input surge currents and glitches at the input during turn-on/turn-off. when uvlo is cleared and en_ is high, digital soft-start slowly ramps up the internal reference voltage in 64 steps. the total soft-start period is 2048 switching cycles of the internal oscillator. to calculate the soft-start period, use the following equation: where f osc is the internal oscillator frequency in hertz, which is twice the switching frequency of each converter. enable the MAX5072 dual converter provides separate enable inputs en1 and en2 to individually control or sequence the output voltages. these active-high enable inputs are ttl compatible. pulling en_ high ramps up the reference slowly, which provides soft-start at the outputs. forcing the en_ low externally disables the individual output and generates a rst signal. use en1, en2, and pgood1 for sequencing (see figure 4). connect pgood1 to en2 to make sure converter 1? output is within regulation before converter 2 starts. add an rc network from vl to en1 and en2 to delay the individual converter. a larger rc time constant means a more delayed output. sequencing reduces input inrush current and possible chattering. connect the en_ to vl for always-on operation. mr microprocessor-based products require manual reset capability, allowing the operator or external logic circuitry to initiate a reset. a logic low on mr asserts reset. reset remains asserted while mr is low, and for the reset active timeout period (t rp ) after mr returns high. mr has an internal 44k ? pullup resistor to vl, so it can be left unconnected if not used. mr can be driven to ttl logic levels. connect a normally open momentary switch from mr to sgnd to create a manual reset function. note that external debounce circuitry is not required. if mr is dri- ven from long cables or if the device is used in a noisy environment, connect a 0.1? capacitor from mr to sgnd to provide additional noise immunity. rst output rst is an open-drain output. rst pulls low when either output falls below 92.5% of its nominal regulation volt- age. once both outputs exceed 92.5% of their nominal regulated voltages and both soft-start cycles are com- pleted, rst enters a high-impedance state after the 180ms active timeout period. to obtain a logic-voltage output, connect a pullup resistor from rst to a logic supply voltage. the internal open-drain mosfet can sink 3ma while providing a ttl logic-low signal. if unused, ground rst or leave it unconnected. pgood1 in addition to rst , converter 1 also includes a power- good flag. pull pgood1 to a logic voltage to provide logic-level output. pgood1 is an open-drain output and can sink 3ma while providing the ttl logic-low signal. pgood1 goes low when converter 1? output drops to 92.5% of its nominal regulated voltage. connect pgood1 to sgnd or leave unconnected, if not used. t f ss osc = 2048
MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output 16 ______________________________________________________________________________________ dying gasp comparator (pfi/pfo) the MAX5072 contains an uncommitted comparator with an open-drain output. the inverting input of the comparator is connected to an internal precision 0.78v reference. connect the noninverting input (pfi) to v in through a resistor-divider to program the input trip threshold (v trip ). the power-fail output (pfo) is pulled low when pfi drops below 0.78v. pfi provides 20mv hysteresis to avoid glitches during transition. the pfo signal provides an advance signal to the processor before the converter 1/converter 2 loses regulation. the input trip threshold (v trip ) can be adjusted to provide advance signaling before the outputs drop to 92.5% of the regulation voltage. the input capacitors hold charge and provide energy to the converter after v in is disconnected. the hold-up time (t hold ) is defined as the time when the input volt- age drops below v trip and the output falls out of regu- lation at the low end of the input voltage range v in(min) (figure 5). use the following equations to calculate the resistor-divider and the c in required for the proper hold-up time. where 1 and 2 are efficiencies of the converter 1 and converter 2, respectively. r 2 can be any value from 10k ? to 100k ? (figure 5). current limit the internal switch current of each converter is sensed using an internal current mirror. converter 1 and con- verter 2 have 2a and 1a internal switches. when the peak switch current crosses the current-limit threshold of 3a (typ) and 1.8a (typ) for converter 1 and converter 2, respectively, the on cycle is terminated immediately and the inductor is allowed to discharge. the next cycle resumes at the next clock pulse. r1 r2 v 0.78 trip 1 = ? ? ? ? ? ? ? c 2 p 1 p 2 vv t in out1 out2 trip 22 in(min) hold = + ? ? ? ? ? ? ? ? ? ? ? ? fb1 fb2 en1 en2 vl r1 r2 c1 c2 vl vl v+ MAX5072 output2 output1 drain2 source2 drain1 source1 v in vl fb1 fb2 en1 en2 sequencing?utput 2 delayed with respect to output 1. r1/c1 and r2/c2 are sized for required sequencing. vl vl vl v+ MAX5072 output2 output1 drain2 source2 drain1 source1 pgood1 v in vl figure 4. power-supply sequencing configurations pfi pfo pfo cin vl vl vl v+ MAX5072 output2 output1 drain2 source2 drain1 source1 v in r1 r2 figure 5. dying gasp feature monitors input supply
MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output ______________________________________________________________________________________ 17 in deep overload or short-circuit conditions when the fb voltage drops below 0.4v, the switching frequency is reduced to 1/4 x f sw to provide sufficient time for the inductor to discharge. during overload conditions, if the voltage across the inductor is not high enough to allow for the inductor current to properly discharge, current runaway may occur. current runaway can destroy the device in spite of internal thermal-overload protection. reducing the switching frequency during overload con- ditions prevents current runaway. thermal-overload protection during continuous short circuit or overload at the out- put, the power dissipation in the ic can exceed its limit. internal thermal shutdown is provided to avoid irre- versible damage to the device. when the die tempera- ture or junction temperature exceeds +150?, an on-chip thermal sensor shuts down the device, forcing the internal switches to turn off, allowing the ic to cool. the thermal sensor turns the part on again after the junction temperature cools by +30?. during thermal shutdown, both regulators shut down, rst goes low, and soft-start resets. applications information setting the switching frequency the controller generates the clock signal by dividing down the internal oscillator or the sync input signal when driven by an external oscillator. the switching frequency equals half the oscillator frequency (f sw = f osc / 2). the internal oscillator frequency is set by a resistor (r osc ) connected from osc to sgnd. the relationship between f sw and r osc is: where f sw and f osc are in hertz, and r osc is in ohms. for example, a 1250khz switching frequency is set with r osc = 10k ? . higher frequencies allow designs with lower inductor values and less output capacitance. consequently, peak currents and i 2 r losses are lower at higher switching frequencies, but core losses, gate- charge currents, and switching losses increase. a rising clock edge on sync is interpreted as a syn- chronization input. if the sync signal is lost, the inter- nal oscillator takes control of the switching rate, returning the switching frequency to that set by r osc . this maintains output regulation even with intermittent sync signals. when an external synchronization signal is used, r osc should be set for the oscillator frequency to be lower than or equal to the sync rate (f sync ). buck converter effective input voltage range although the MAX5072 converters can operate from input supplies ranging from 4.5v to 23v, the input volt- age range can be effectively limited by the MAX5072 duty-cycle limitations for a given output voltage. the maximum input voltage is limited by the minimum on- time (t on(min) ): where t on(min) is 100ns. the minimum input voltage is limited by the maximum duty cycle (d max = 0.88): where v drop1 is the total parasitic voltage drops in the inductor discharge path, which includes the forward voltage drop (v d ) of the rectifier, the series resistance of the inductor, and the pc board resistance. v drop2 is the total resistance in the charging path, which includes the on-resistance of the high-side switch, the series resistance of the inductor, and the pc board resistance. setting the output voltage for 0.8v or greater output voltages, connect a voltage- divider from out_ to fb_ to sgnd (figure 6). select r b (fb_ to sgnd resistor) to between 1k ? and 10k ? . calculate r a (out_ to fb_ resistor) with the following equation: where v fb_ = 0.8v (see the electrical characteristics table) and v out_ can range from v fb_ to 28v (boost operation). rr v v ab out fb = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 v vv vv in min out drop drop drop () . = + ? ? ? ? ? ? + ? 1 21 088 v v tf in max out on min sw () () r 12.5 10 f osc 9 sw = r a lx_ fb_ v out_ > 0.8v r b MAX5072 r c fb_ lx_ bypass v out_ < 0.8v r a MAX5072 figure 6. adjustable output voltage
MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output 18 ______________________________________________________________________________________ for output voltages below 0.8v, set the MAX5072 out- put voltage by connecting a voltage-divider from the output to fb_ to bypass (figure 6). select r c (fb to bypass resistor) higher than a 50k ? range. calculate r a with the following equation: where v fb = 0.8v, v bypass = 2v (see the electrical characteristics table), and v out_ can range from 0v to v fb_ . inductor selection three key inductor parameters must be specified for operation with the MAX5072: inductance value (l), peak inductor current (i l ), and inductor saturation current (i sat ). the minimum required inductance is a function of operating frequency, input-to-output voltage differential and the peak-to-peak inductor current ( ? i l ). higher ? i l allows for a lower inductor value while a lower ? i l requires a higher inductor value. a lower inductor value minimizes size and cost, improves large-signal transient response, but reduces efficiency due to higher peak cur- rents and higher peak-to-peak output ripple voltage for the same output capacitor. on the other hand, higher inductance increases efficiency by reducing the ripple current. however, resistive losses due to extra wire turns can exceed the benefit gained from lower ripple current levels, especially when the inductance is increased with- out also allowing for larger inductor dimensions. a good compromise is to choose ? i l equal to 30% of the full load current. to calculate the inductance use the follow- ing equation: where v in and v out are typical values (so that efficiency is optimum for typical conditions). the switching frequen- cy is set by r osc (see the setting the switching frequency section). the peak-to-peak inductor current, which reflects the peak-to-peak output ripple, is worst at the maximum input voltage. see the output capacitor selection section to verify that the worst-case output rip- ple is acceptable. the inductor saturating current is also important to avoid runaway current during the output overload and continuous short circuit. select the i sat to be higher than the maximum peak current limits of 4.5a and 2.2a for converter 1 and converter 2. input capacitors the discontinuous input current waveform of the buck converter causes large ripple currents at the input. the switching frequency, peak inductor current, and the allowable peak-to-peak voltage ripple dictate the input capacitance requirement. increasing the switching fre- quency or the inductor value lowers the peak to aver- age current ratio, yielding a lower input capacitance requirement. note that two converters of MAX5072 run 180 out-of-phase, thereby effectively doubling the switching frequency at the input. the input ripple waveform would be unsymmetrical due to the difference in load current and duty cycle between converter 1 and converter 2. the input ripple is com- prised of ? v q (caused by the capacitor discharge) and ? v esr (caused by the esr of the capacitor). a higher load converter dictates the esr requirement, while the capacitance requirement is a function of the loading mismatch between the two converters. the worst-case mismatch is when one converter is at full load while the other is at no load or in shutdown. use low-esr ceramic capacitors with high ripple-current capability at the input. assume the contribution from the esr and capac- itor discharge equal to 50%. calculate the input capaci- tance and esr required for a specified ripple using the following equations: where and where where i out is the maximum output current from either converter 1 or converter 2, and d is the duty cycle for that converter. f sw is the frequency of each individual converter. for example, at v in = 12v, v out = 3.3v at i out = 2a, and with l = 3.3?, the esr and input capacitance are calculated for a peak-to-peak input d v v out in = c idd vf in out qsw = ? () 1 ? ? i vv v vf l l in out out in sw = ? () esr v i i in esr out l = + ? ? ? ? ? ? ? ? 2 l vvv vf i out in out in sw l = ? () ? rr vv vv ac fb out bypass fb = ? ? ? ? ? ? ? ?
MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output ______________________________________________________________________________________ 19 ripple of 100mv or less, yielding an esr and capaci- tance value of 20m ? and 6.8? for 1.25mhz frequency. use a 100? capacitor at low input voltages to avoid possible undershoot below the undervoltage lockout threshold during power-on and transient loading. output capacitor selection the allowable output ripple voltage and the maximum deviation of the output voltage during step load currents determines the output capacitance and its esr. the output ripple is comprised of ? v q (caused by the capacitor discharge) and ? v esr (caused by the esr of the capacitor). use low-esr ceramic or aluminum elec- trolytic capacitors at the output. for aluminum electrolytic capacitors, the entire output ripple is contributed by ? v esr . use the esr out equation to calculate the esr requirement and choose the capacitor accordingly. if using ceramic capacitors, assume the contribution to the output ripple voltage from the esr and the capacitor discharge are equal. calculate the output capacitance and esr required for a specified ripple using the follow- ing equations: where where ? i l is the peak-to-peak inductor current as cal- culated above and f sw is the individual converter? switching frequency. the allowable deviation of the output voltage during fast transient loads also determines the output capaci- tance and its esr. the output capacitor supplies the step load current until the controller responds with a greater duty cycle. the response time (t response ) depends on the closed-loop bandwidth of the convert- er. the high switching frequency of MAX5072 allows for higher closed-loop bandwidth, reducing t response and the output capacitance requirement. the resistive drop across the output capacitor esr and the capaci- tor discharge causes a voltage droop during a step load. use a combination of low-esr tantalum and ceramic capacitors for better transient load and ripple/noise performance. keep the maximum output voltage deviation above the tolerable limits of the elec- tronics being powered. when using a ceramic capaci- tor, assume 80% and 20% contribution from the output capacitance discharge and the esr drop, respectively. use the following equations to calculate the required esr and capacitance value: where i step is the load step and t response is the response time of the controller. controller response time depends on the control-loop bandwidth. boost converter the MAX5072 can be configured for step-up conversion since the internal mosfet can be used as a low-side switch. use the following equations to calculate the inductor (l min ), input capacitor (c in ), and output capac- itor (c out ) when using the converter in boost operation. inductor choose the minimum inductor value so the converter remains in continuous mode operation at minimum out- put current (i omin ). where and i omin = 0.25 x i o the v d is the forward voltage drop of the external schottky diode, d is the duty cycle, and v ds is the voltage drop across the internal switch. select the inductor with low dc resistance and with a saturation current (i sat ) rating high- er than the peak switch current limit of 4.5a and 2.2a of converter 1 and converter 2, respectively. input capacitor the input current for the boost converter is continuous and the rms ripple current at the input is low. calculate the capacitor value and esr of the input capacitor using the following equations. d vvv vvv odin odds = + ? + ? l vd fvi min in sw o omin = 2 2 c it v out step response q = ? esr v i out esr step = ? ??? vvv o ripple esr q _ ? + c i vf out l qsw = ? ? 8 esr v i out esr l = ? ?
MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output 20 ______________________________________________________________________________________ where where v ds is the total voltage drop across the internal mosfet plus the voltage drop across the inductor esr. ? i l is the peak-to-peak inductor ripple current as calculated above. ? v q is the portion of input ripple due to the capacitor discharge and ? v esr is the contribu- tion due to esr of the capacitor. output capacitor selection for the boost converter, the output capacitor supplies the load current when the main switch is on. the required output capacitance is high, especially at high- er duty cycles. also, the output capacitor esr needs to be low enough to minimize the voltage drop due to the esr while supporting the load current. use the follow- ing equation to calculate the output capacitor for a specified output ripple tolerance. i o is the load current, ? v q is the portion of the ripple due to the capacitor discharge and ? v esr is the contri- bution due to the esr of the capacitor. d max is the maximum duty cycle at minimum input voltage. power dissipation the MAX5072 includes a high-frequency, low r ds_on switching mosfet. at +85?, the r ds_on of the inter- nal switch for converter 1 and converter 2 are 290m ? and 630m ? , respectively. the dc loss is a function of the rms current in the switch while the switching loss is a function of switching frequency and input voltage. use the following equations to calculate the rms current, dc loss, and switching loss of each converter. the MAX5072 device is available in a thermally enhanced package and can dissipate up to 2.7w at +70? ambi- ent temperature. the total power dissipation in the pack- age must be limited so the junction temperature does not exceed its absolute maximum rating of +150? at maxi- mum ambient temperature. for the buck converter: where see the electrical characteristics table for the r ds(on)max value. i pk =+ i i o l ? 2 i dc = ? i i o l ? 2 pi r dc rms ds(on)max 2 = ii+i+(ii d 3 rms dc pk dc pk max 22 = ()) c id vf out o max qsw = ? esr v i esr o = ? ? i vv d lf l in ds sw = ? () esr v i esr l = ? ? c id fv in l sw q = ? ? 4 r 1 r f comp v out v ref c cf c f r 2 - + g m figure 7. type ii compensation network. r1 r f comp v out v ref r2 r i c i c f c cf - + g m figure 8. type iii compensation network
MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output ______________________________________________________________________________________ 21 for the boost converter: where v ds is the drop across the internal mosfet. see the electrical characteristics for the r ds(on)max value. where t r and t f are rise and fall times of the internal mosfet. the t r and t f are typically 20ns, and can be measured in the actual application. the supply current in the MAX5072 is dependent on the switching frequency. see the typical operating characteristics to find the supply current of the MAX5072 at a given operating frequency. the power dissipation (p s ) in the device due to supply current (i s ) is calculated using following equation. the total power dissipation p t in the device is: p t = p dc1 + p dc2 + p sw1 + p sw2 + p s where p dc1 and p dc2 are dc losses in converter 1 and converter 2, respectively. p sw1 and p sw2 are switching losses in converter 1 and converter 2, respectively. calculate the temperature rise of the die using the fol- lowing equation: t j = t c + (p t x j-c ) where j-c is the junction-to-case thermal impedance of the package equal to +2 c/w. solder the exposed pad of the package to a large copper area to minimize the case-to-ambient thermal impedance. measure the temperature of the copper area near the device at a worst-case condition of power dissipation and use +2 c/w as j-c thermal impedance. the case-to-ambi- ent thermal impedance ( c-a ) is dependent on how well the heat is transferred from the pc board to the ambient. use large copper area to keep the pc board temperature low. the c-a is usually in the +20 c/w to +40 c/w range. compensation the MAX5072 provides an internal transconductance amplifier with its inverting input and its output available to the user for external frequency compensation. the flexibility of external compensation for each converter offers wide selection of output filtering components, especially the output capacitor. for cost-sensitive applications, use high-esr aluminum electrolytic capacitors; for component size-sensitive applications, use low-esr tantalum or ceramic capacitors at the out- put. the high switching frequency of MAX5072 allows use of ceramic capacitors at the output. choose all the passive power components that meet the output ripple, component size, and component cost requirements. choose the small-signal components for the error amplifier to achieve the desired closed-loop bandwidth and phase margin. use a simple pole-zero pair (type ii) compensation if the output capacitor esr zero frequency is below the unity-gain crossover fre- quency (f c ). type iii compensation is necessary when the esr zero frequency is higher than f c or when com- pensating for a continuous mode boost converter that has a right-half plane zero. use the following procedure 1 to calculate the compen- sation network components when f zero,esr < f c . buck converter compensation procedure 1 (see figure 7): calculate the f zero,esr and lc double pole: pv i s inmax supply = p sw = + vi t t f oin r f sw () 4 pi r dc rms ds(on)max 2 = i pk =+ i i in l ? 2 i dc = ? i i in l ? 2 ? i vv d lf l in ds sw = ? () i vi v in oo in = ii+i+(ii d 3 rms dc pk dc pk max 22 = ()) p sw = + vittf inmax o r f sw () 4
MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output 22 ______________________________________________________________________________________ calculate the unity-gain crossover frequency as: if the f zero,esr is lower than f c and close to f lc , use a type ii compensation network where r f c f provides a midband zero f mid,zero , and r f c cf provides a high-fre- quency pole. calculate modulator gain g m at the crossover frequency. where v osc is a peak-to-peak ramp amplitude equal to 1v. g v v esr esr f l v m in osc c out out = + 2 08 . f f c sw = 20 f esr c f lc zero esr out lc out out , = = 1 2 1 2 pgood1 clock out output 2.5v/1a output 3.3v/2a vl vl vl pgnd sgnd pfo system clock v in = 5.5v to 23v p reset input 32 31 30 29 28 27 26 9 101112131415 18 19 20 21 22 23 24 7 6 5 4 3 2 1 bst2/vdd2 clkout drain2 drain2 en2 on off fb2 comp2 8 pfo source2 pgnd sgnd pgnd source1 25 pgood1 fsel1 bst1/vdd1 drain1 drain1 en1 fb1 comp1 17 rst bypass vl 16 mr manual reset vl v+ osc pfi sync on off vout1 sgnd* vl dying gasp *connect pgnd and sgnd together at one point near the return terminals of the v+ and vl bypass capacitors. ep MAX5072 sgnd figure 9. buck-boost application
MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output ______________________________________________________________________________________ 23 the transconductance error-amplifier gain is: the total loop gain at f c should be equal to 1 or place a zero at or below the lc double pole: place a high-frequency pole at f p = 0.5 x f sw . procedure 2 (see figure 8): if the output capacitor used is a low-esr ceramic type, the esr frequency is usually far away from the targeted unity crossover frequency (f c ). in this case, type iii com- pensation is recommended. type iii compensation pro- vides two-pole zero pairs. the locations of the zero and poles should be such that the phase margin peaks at f c . the is a good number to get about 60 phase margin at f c . however, it is important to place the two zeros at or below the double pole to avoid the conditional stability issue. select a crossover frequency: calculate the lc double-pole frequency, f lc : place a zero where: and r f 10k ? . calculate c i for a target unity crossover frequency, f c : place a pole at f zero,esr . place a second zero, f z2 , at 0.2f c or at f lc , whichever is lower. place a second pole at 1/2 the switching frequency. boost converter compensation the boost converter compensation gets complicated due to the presence of a right-half-plane zero f zero,rhp . the right-half-plane zero causes a drop in- phase while adding positive (+1) slope to the gain curve. it is important to drop the gain significantly below unity before the rhp frequency. use the following procedure to calculate the compensation components. calculate the lc double-pole frequency, f lc , and the right half plane zero frequency. where: target the unity-gain crossover frequency for: d v v r v i in out min out out max = ? = 1 () () f d lc f dr l lc out out zero rhp min out = ? = ? 1 2 1 2 2 , () () c c frc cf f sw f f = ? (. ) 205 1 () f rc p fcf 2 1 2 = r fc r zi i 1 1 2 2 = ? r fc i zero esr i = 1 2 , (f rc p ii 1 1 2 = c fl c v vr i c out out osc in f = 2 c fr f lc f = 1 2075 . f rc at f z ff lc = 1 2 075 . f lc lc out out = 1 2 f f c sw 20 f f f f c z p c == 5 c rf f flc = 1 2 r v esr f l v v g esr f osc c out out in m = + () . 2 08 gg mea = / 1 ggr ea m f / =
MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output 24 ______________________________________________________________________________________ place a zero at 0.75 x f lc . where r f 10k ? . calculate c i for a target crossover frequency, f c : where c = 2 f c . place a pole at f zero,rhp . place the second zero at f lc . place the second pole at 1/2 the switching frequency. improving noise immunity in applications where the MAX5072 are subject to noisy environments, adjust the controller? compensation to improve the system? noise immunity. in particular, high-frequency noise coupled into the feedback loop causes jittery duty cycles. one solution is to lower the crossover frequency (see the compensation section). pc board layout guidelines careful pc board layout is critical to achieve low switching losses and clean, stable operation. this is especially true for dual converters where one channel can affect the other. refer to the MAX5072 ev kit data sheet for a specific layout example. use a multilayer board whenever possible for better noise immunity. follow these guidelines for good pc board layout: 1) for sgnd, use a large copper plane under the ic and solder it to the exposed paddle. to effectively use this copper area as a heat exchanger between the pc board and ambient, expose this copper area on the top and bottom side of the pc board. do not make a direct connection from the exposed pad copper plane to sgnd (pin 29) underneath the ic. 2) isolate the power components and high-current path from the sensitive analog circuitry. use a sep- arate pgnd plane under the out1 and out2 sides (referred to as pgnd1 and pgnd2). connect the pgnd1 and pgnd2 planes together at one point near the ic. 3) keep the high-current paths short, especially at the ground terminals. this practice is essential for sta- ble, jitter-free operation. 4) connect sgnd and pgnd together close to the ic at the ground terminals of vl and v+ bypass capac- itors. do not connect them together anywhere else. 5) keep the power traces and load connections short. this practice is essential for high efficiency. use thick copper pc boards (2oz vs. 1oz) to enhance full-load efficiency. 6) ensure that the feedback connection to c out is short and direct. 7) route high-speed switching nodes (bst_/vdd_, source_) away from the sensitive analog areas (bypass, comp_, and fb_). use the internal pc board layer for sgnd as emi shields to keep radiat- ed noise away from the ic, feedback dividers, and analog bypass capacitors. c c frc cf f sw f f = ? (. ) 205 1 () f rc p fcf 2 1 2 = r fc r lc i i 1 1 2 = ? () f rc z i 2 1 1 2 = r fc i zero rhp i = 1 2 , () f rc p ii 1 1 2 = c vd lc rv i osc c o o cfin = + ? ? ? ? ? ? ? ? ? () 1 2 2 c fr f lc f = 1 2075 . () f rc z ff 1 1 2 = f f c zero rhp , 5
MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output ______________________________________________________________________________________ 25 layout procedure 1) place the power components first, with ground ter- minals adjacent (inductor, c in_ , and c out_ ). make all these connections on the top layer with wide, copper-filled areas (2oz copper recommended). 2) group the gate-drive components (bootstrap diodes and capacitors, and vl bypass capacitor) together near the controller ic. 3) make the dc-dc controller ground connections as follows: a) create a small-signal ground plane underneath the ic. b) connect this plane to sgnd and use this plane for the ground connection for the reference (bypass), enable, compensation components, feedback dividers, and osc resistor. c) connect sgnd and pgnd together near the input bypass capacitors and the ic (this is the only connection between sgnd and pgnd). chip information transistor count: 5994 process: bicmos ordering information (continued) * ep = exposed pad. + denotes lead-free package. part temp range pin-package pkg code m ax5072e tj+ -40 c to +85 c 32 thin qfn-ep* (5mm x 5mm) t3255-4 MAX5072atj -40 c to +125 c 32 thin qfn-ep* (5mm x 5mm) t3255-4 m ax5072atj+ -40 c to +125 c 32 thin qfn-ep* (5mm x 5mm) t3255-4
MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output 26 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) qfn thin.eps
MAX5072 2.2mhz, dual-output buck or boost converter with por and power-fail output maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 27 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)

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